SRAM devices are known in the art for high speed memory applications, such as high performance processor caches. The structure of a conventional SRAM cell comprises two cross-coupled inverters, typically formed from four Complementary Metal Oxide Semiconductor (“Complementary MOS” or “CMOS”) transistors. The cross-coupled inverters form the basic storage element, with two stable states which represent the complementary binary values “0” and “1”. Two access transistors, serve to control access to the storage element during read and write operations. Accordingly, a conventional SRAM cell architecture involves six transistors, and is generally referred to as a 6T SRAM cell.
FIG. 1 illustrates a conventional 6T SRAM cell 100. The storage element comprises transistors M1-M4. A write operation on cell 100 is initiating by driving a 0 or 1 through complementary bitlines BL and BLB and word line WL to positive power supply voltage VDD. Access transistors M5 and M6 write the values on complementary bitlines into the storage element. In a read operation, complementary bitlines BL and BLB are both precharged to a predefined value, usually, VDD. Once word line WL is activated, the complementary values stored in the storage element act to discharge one of the complementary bitlines, say BL, while the other complementary bitline BLB is maintained at the precharge voltage. Sense amplifiers (not shown) quickly detect the differential values of the discharged bitline BL and the precharged complementary bitline BLB and read out a 0 accordingly.
With shrinking device sizes in nanometer technologies, the MOS transistors used in conventional 6T SRAM cell 100 are subject to increasing demands for meeting performance targets. However, the SRAM circuitry is restrained to low operating voltages, in order to reduce power consumption. Random doping fluctuations limit the operation of SRAM cells at low operating voltages. The combination of small device sizes and low operating voltages causes memory devices such as SRAM to lag behind speed and performance metrics of other logic circuits in processing systems.
One approach to overcome the above limitations of 6T SRAMs includes an 8-transistor (8T) configuration for SRAM cells. FIG. 2 illustrates a conventional 8T SRAM cell 200. As illustrated, transistors M7 and M8 are added to a 6T SRAM cell circuit, such as 6T SRAM cell 100, in order to improve performance during read access operation. Accordingly, the eight transistors, M1-M8 form 8T SRAM cell 200. During write operations, write word line WWL is enabled. Write word line WWL and complementary write bitlines WBL and WBLB are coupled to the storage element (transistors M1-M4) through write access transistors M5 and M6. During read operations, read word line RWL is enabled, and read access transistors M7 and M8 couple the storage element to read bitline RBL. Thus, in contrast to 6T SRAM cell 100, 8T SRAM cell 200 provides separate access paths to the storage element during read and write operations.
Precharge transistors M9, M10, and M11 are configured to precharge write bitlines WBL and WBLB, and read bitline RBL. The write and read bitlines are precharged when 8T SRAM cell 200 is inactive, or in sleep mode. Precharging 8T SRAM cell 200 in this manner, overcomes some of the limitations associated with low operating voltage and low performance for 6T SRAMs as described above.
However, conventional implementations of 8T SRAM cells, such as 8T SRAM cell 200, suffer from additional drawbacks. For instance, the leakage current of 8T SRAM cell 200 is much higher than the leakage current of 6T SRAM cell 100. Because precharge transistors M9, M10, and M11 are configured for precharging the write and read bitlines, these precharge transistors are always turned on when 8T SRAM cell 200 is inactive or in standby mode. As a result, these precharge transistors give rise to leakage paths 202, 204, and 206 as shown. Leakage path 202 arising from precharging write bitline WBL is formed from VDD to ground through transistors M9, M5, and M3 as shown. Similarly, leakage path 204 arising from precharging write bitline WBLB is formed from VDD to ground through transistors M10, M6, and M4. Finally, leakage path 206 arising from precharging read bitline RBL is formed from VDD to ground through transistors M11, M7, and M8.
The leakage paths 202, 204, and 206 result in wastage of power and performance degradation. Accordingly, there is a need in the art for 8T SRAM cell designs which overcome the aforementioned drawbacks of conventional 8T SRAM implementations.